{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":667379968,"defaultBranch":"main","name":"generating-VHDL-and-Verilog-code-for-full-adder-using-MATLAB-HDL-coder","ownerLogin":"Akul-Verma","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2023-07-17T11:24:22.000Z","ownerAvatar":"https://github.com/avatars/u/92621469?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1689593202.0","currentOid":""},"activityList":{"items":[{"before":null,"after":"ae652a0b28c4ca822329b033855feffec95cca73","ref":"refs/heads/main","pushedAt":"2023-07-17T11:26:42.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Akul-Verma","name":"Akul Verma","path":"/Akul-Verma","primaryAvatarUrl":"https://github.com/avatars/u/92621469?s=80&v=4"},"commit":{"message":"Add files via upload","shortMessageHtmlLink":"Add files via upload"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"Y3Vyc29yOnYyOpK7MjAyMy0wNy0xN1QxMToyNjo0Mi4wMDAwMDBazwAAAANW-tEN","startCursor":"Y3Vyc29yOnYyOpK7MjAyMy0wNy0xN1QxMToyNjo0Mi4wMDAwMDBazwAAAANW-tEN","endCursor":"Y3Vyc29yOnYyOpK7MjAyMy0wNy0xN1QxMToyNjo0Mi4wMDAwMDBazwAAAANW-tEN"}},"title":"Activity ยท Akul-Verma/generating-VHDL-and-Verilog-code-for-full-adder-using-MATLAB-HDL-coder"}