{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":667628479,"defaultBranch":"main","name":"Verification-of-UART-communication-protocol-design-using-System-Verilog","ownerLogin":"Akul-Verma","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2023-07-18T00:38:44.000Z","ownerAvatar":"https://github.com/avatars/u/92621469?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1699345401.0","currentOid":""},"activityList":{"items":[{"before":"c2fec520e7e72893f001ca3f67f5094fa643836b","after":"48d8cab00d9f1b48c19f6d47dd7cf4e9e5bdf07d","ref":"refs/heads/main","pushedAt":"2023-11-07T08:23:21.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Akul-Verma","name":"Akul Verma","path":"/Akul-Verma","primaryAvatarUrl":"https://github.com/avatars/u/92621469?s=80&v=4"},"commit":{"message":"Add files via upload","shortMessageHtmlLink":"Add files via upload"}},{"before":"72c666ad8d4d3abc7eecab578b52ad953502ed84","after":"c2fec520e7e72893f001ca3f67f5094fa643836b","ref":"refs/heads/main","pushedAt":"2023-11-07T08:22:13.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Akul-Verma","name":"Akul Verma","path":"/Akul-Verma","primaryAvatarUrl":"https://github.com/avatars/u/92621469?s=80&v=4"},"commit":{"message":"Delete Theory and Flowchart.pdf","shortMessageHtmlLink":"Delete Theory and Flowchart.pdf"}},{"before":"bc49fb6bcee8b41e96a16190333246b0e683f7e2","after":"72c666ad8d4d3abc7eecab578b52ad953502ed84","ref":"refs/heads/main","pushedAt":"2023-11-07T08:21:15.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Akul-Verma","name":"Akul Verma","path":"/Akul-Verma","primaryAvatarUrl":"https://github.com/avatars/u/92621469?s=80&v=4"},"commit":{"message":"Add files via upload","shortMessageHtmlLink":"Add files via upload"}},{"before":null,"after":"bc49fb6bcee8b41e96a16190333246b0e683f7e2","ref":"refs/heads/main","pushedAt":"2023-07-18T00:47:00.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Akul-Verma","name":"Akul Verma","path":"/Akul-Verma","primaryAvatarUrl":"https://github.com/avatars/u/92621469?s=80&v=4"},"commit":{"message":"Add files via upload","shortMessageHtmlLink":"Add files via upload"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAADqSGmxAA","startCursor":null,"endCursor":null}},"title":"Activity ยท Akul-Verma/Verification-of-UART-communication-protocol-design-using-System-Verilog"}