{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":668451828,"defaultBranch":"main","name":"-Verifying-4-bit-Multiplier-design-using-System-Verilog","ownerLogin":"Akul-Verma","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2023-07-19T20:58:07.000Z","ownerAvatar":"https://github.com/avatars/u/92621469?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1689802204.0","currentOid":""},"activityList":{"items":[{"before":"b9b9c27b743fc2269aa6f06f1c573ce4793023a9","after":"3a796da8bb107d4eae43363dcdea9c6963d2ede3","ref":"refs/heads/main","pushedAt":"2023-07-19T21:30:05.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Akul-Verma","name":"Akul Verma","path":"/Akul-Verma","primaryAvatarUrl":"https://github.com/avatars/u/92621469?s=80&v=4"},"commit":{"message":"Add files via upload","shortMessageHtmlLink":"Add files via upload"}},{"before":null,"after":"b9b9c27b743fc2269aa6f06f1c573ce4793023a9","ref":"refs/heads/main","pushedAt":"2023-07-19T20:58:34.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Akul-Verma","name":"Akul Verma","path":"/Akul-Verma","primaryAvatarUrl":"https://github.com/avatars/u/92621469?s=80&v=4"},"commit":{"message":"Add files via upload","shortMessageHtmlLink":"Add files via upload"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAADWRoIHwA","startCursor":null,"endCursor":null}},"title":"Activity ยท Akul-Verma/-Verifying-4-bit-Multiplier-design-using-System-Verilog"}